The present invention is generally directed to a central processor for use in a telephone exchange switching system and in particular to a central processor for use in a telephone switching system wherein the subsystems of the system are interconnected on a common data bus.
Modern telephone exchanges operate in response to a central processor which controls all of the necessary functions within the exchange system to provide requested service. One type of well known exchange system is disclosed in Borbas et al, U.S. Pat. No. 3,767,863 which issued on Oct. 23, 1973 and which is assigned to the assignee of the present invention. The exchange system theredisclosed is a system wherein the subsystems of the exchange are interconnected on a common data bus and each has an interface unit so that it may be specifically addressed. Among the subsystems is a program memory which contains the operational codes to be utilized by the central processor to control the overall function of the system.
Each of the subsystems is interfaced to the central processor by a bus control unit which is fully disclosed and claimed in Borbas, U.S. Pat. No. 3,812,297 which is also assigned to the assignee of the present invention. The bus control unit theredescribed is one which is compatible with the present invention. Any further reference to a bus control unit may be made to the aforementioned U.S. Pat. No. 3,812,297. The bus control unit theredescribed provides an address cycle followed by a data cycle indicated by signals on the control conductors for use by the central processor.
To control the operation of a telephone exchange such as the one disclosed in the aforementioned U.S. Pat. No. 3,767,863, a central processor is required. It operates under commnad of operational codes to control the function of the subsystems connected to the common data bus to provide the desired service between the subscribers.
It is therefore an object of the present invention to provide an improved central processor for telephone exchange systems.
It is a further object of the present invention to provide a central processor for controlling the operations of the subsystems of a telephone exchange system which are interconnected onto a data bus.
It is a still further object of the present invention to provide a central processor which controls the function of the system subsystems under command of operational codes provided by a program memory within the system and wherein the operational codes are selectable in response to the particular service desired.
The present invention provides a central processor for controlling the operation of subsystems which are interconnected on a common data bus of a telephone exchange to establish requested service between telephone subscribers, wherein the exchange includes a program memory also connected to the common data bus for storing a plurality of addressable multiple bit operational codes to be utilized by the central processor in response to the particular service being requested. The central processor includes a program address register for storing the program memory address of a selected operational code and for addressing the program memory to cause it to transmit the selected operational code over the common data bus. The central processor also includes an instruction register for storing the selected operational code and for providing subsystem address signals responsive to the selected operational code, an arithmetic logic unit coupled to the instruction register for transmitting the subsystem address signals, the arithmetic logic unit additionally being coupled to the common data bus for transferring the selected operational code from the program memory to the instruction register, and for performing logic and arithmetic functions responsive to function control signals to provide subsystem data and operation signals, a bus address register coupled between the arithmetic logic unit and the common data bus for storing the address of a selected subsystem responsive to the subsystem address signals, a bit time counter for providing operational timing signals and a control word generator coupled to the instruction register for providing the function control signals responsive to the selected operational code stored in the instruction register and coupled to the bit time counter for coacting therewith to provide the function control signals in proper time sequence.